Digital Hardware & Semiconductor Design — Skills Plan
Planned skill map for Digital Hardware & Semiconductor Design. The curriculum will be developed and released in stages.
Study digital logic and computer architecture, write and verify RTL, prototype on FPGA, and examine timing, synthesis, physical design, and silicon testing.
Potential roles: Digital Design Engineer · RTL Engineer · Design Verification Engineer · FPGA Engineer
Before you start
- Boolean algebra and binary arithmetic
- Basic circuit theory
- Programming and structured debugging
What you’ll build
- Implement and verify a small RTL block
- Prototype a controller on an FPGA
- Analyze timing and verification coverage
Prerequisites
PLANNED- Boolean algebra and binary arithmetic
Build the Boolean algebra and binary arithmetic knowledge needed to follow the Digital Hardware & Semiconductor Design foundations.
- Basic circuit theory
Build the Basic circuit theory knowledge needed to follow the Digital Hardware & Semiconductor Design foundations.
- Programming and structured debugging
Build the Programming and structured debugging knowledge needed to follow the Digital Hardware & Semiconductor Design foundations.
Foundations
PLANNED- Combinational and sequential logic
Explain how Combinational and sequential logic works and where it fits in the Digital Hardware & Semiconductor Design learning path.
- Finite-state machines and timing
Explain how Finite-state machines and timing works and where it fits in the Digital Hardware & Semiconductor Design learning path.
- Computer organization and datapaths
Explain how Computer organization and datapaths works and where it fits in the Digital Hardware & Semiconductor Design learning path.
- HDL concepts with Verilog/SystemVerilog
Explain how HDL concepts with Verilog/SystemVerilog works and where it fits in the Digital Hardware & Semiconductor Design learning path.
Core Skills
PLANNED- RTL design and simulation
Use RTL design and simulation to implement a working capability and verify its behavior in Digital Hardware & Semiconductor Design.
- Testbench development and assertions
Use Testbench development and assertions to implement a working capability and verify its behavior in Digital Hardware & Semiconductor Design.
- FPGA synthesis and timing constraints
Use FPGA synthesis and timing constraints to implement a working capability and verify its behavior in Digital Hardware & Semiconductor Design.
- Bus protocols and interface design
Use Bus protocols and interface design to implement a working capability and verify its behavior in Digital Hardware & Semiconductor Design.
Advanced / Production
PLANNED- Design verification and coverage closure
Evaluate Design verification and coverage closure trade-offs against the performance, reliability, and safety needs of Digital Hardware & Semiconductor Design systems.
- Synthesis, timing, and power trade-offs
Evaluate Synthesis, timing, and power trade-offs trade-offs against the performance, reliability, and safety needs of Digital Hardware & Semiconductor Design systems.
- Physical design and fabrication flow concepts
Evaluate Physical design and fabrication flow concepts trade-offs against the performance, reliability, and safety needs of Digital Hardware & Semiconductor Design systems.
- Design-for-test and silicon validation
Evaluate Design-for-test and silicon validation trade-offs against the performance, reliability, and safety needs of Digital Hardware & Semiconductor Design systems.
- Hardware security and supply-chain awareness
Evaluate Hardware security and supply-chain awareness trade-offs against the performance, reliability, and safety needs of Digital Hardware & Semiconductor Design systems.
Real-World Projects
PLANNED- Implement and verify a small RTL block
Deliver a working outcome with Implement and verify a small RTL block, then test it against the project requirements.
- Prototype a controller on an FPGA
Deliver a working outcome with Prototype a controller on an FPGA, then test it against the project requirements.
- Analyze timing and verification coverage
Deliver a working outcome with Analyze timing and verification coverage, then test it against the project requirements.
Career / Interview Preparation
PLANNED- Digital logic and timing problems
Explain your approach to Digital logic and timing problems, defend key trade-offs, and discuss what you learned.
- RTL review and verification walkthrough
Explain your approach to RTL review and verification walkthrough, defend key trade-offs, and discuss what you learned.
- Hardware design portfolio
Explain your approach to Hardware design portfolio, defend key trade-offs, and discuss what you learned.
Discussion
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